In recent years, since the circuit devices in a chip are manufactured with a high density and it has been a trend to make semiconductor devices having small size. IC (integrated circuits) designers are continuously tempted to scale down the size of each device and increase chip level integration in per unit area. Typically, the semiconductor devices require protection from moisture and mechanical damage. The protection is provided by a package having electrical conductive means to transfer signal between the chip and the external circuits. The renewed interest in high density hybrid is driven by the requirement to handle large numbers of IC interconnections, the increasing clock rate of digital systems and the desire to pack greater functionality into smaller spaces. Therefore, the number of a package's leads becomes more and more. An important consideration in making small, high speed and high-density devices is providing packages capable of the spreading heat generated by the devices. A further problem confronting the technology is the relentless need for more I/O per chip. Those issues lead to the requirement of more power for devices and the reduction of impedance of inductance. A conventional lead frame package has a limitation to increase the number of the package's lead.
FIG. 1 shows a conventional package which includes a substrate 2, a die 4 formed on the substrate via die attach epoxy 6. The die is electrically connected to the substrate 2 by using gold wire bonds 8. Solder balls 10 for signal transfer is formed on the bottom surface of the substrate 2. Molding compound 12 is used to cover the die 4 and gold wire bonds 8 for protection. The heat is spread by using thermal vias 14 formed in the substrate 2 and thermal balls 16 connected to the thermal vias 14. However, the amount heat generated by devices is increased due to the packing density is increased. This also causes the conventional package can not meet the requirement of the future demands.
As the semiconductor production continuously grows, more types of package are developed. One of the notable is the plastic molded package, such as described in U.S. Pat. No. 5,586,010. Another type of package is disclosed in U.S. Pat. No. 5,629,835 to Mahulikar et al., entitled "METAL BALL GRID ARRAY PACKAGE WITH IMPROVED THERMAL CONDUCTIVITY".
VLSI integrated circuits packages having high connection capacity are pin grid array (PGA) and ball grid array (BGA). One such package type is plastic ball grid array (PBGA). The PBGA offers many advantages over conventional packages such as solder ball I/O and high speed. The PBGA package has high speed due to a short path for signal transformation. The solder balls are set on a package surface in a matrix array which can provide more signal contacts.
In order to solve the problem relating to spread heat, pad array semiconductor devices have been proposed (see U.S. Pat. No. 5,285,352). The structure uses a thermal conductor in a pad array device permits routing of conductive traces and terminals beneath a semiconductor die for improved utilization of substrate area. An opening and a thermal conductor are set under the die on a substrate. The heat that is generated by devices is dissipated to computer board via silver epoxy, the opening and a metal ground plane.
The efficiency of spreading heat of the conventional structure is poor. The electrical magnetic (EM) shielding of the prior art is also not good. Thus, what is required is an improved package with good efficiency of spreading heat and EM shielding.